Non-volatile memory cells that are electrically programmable and erasable can be realized as charge-trapping memory cells which comprise a memory layer sequence of dielectric materials with a memory layer between confinement layers of dielectric material having a larger energy bend gap than the memory layer. This memory layer sequence is arranged between a channel region within a semiconductor layer or substrate and a gate electrode, which is provided to control the channel by means of an applied electric voltage. The programming of the cell is performed by the acceleration of charge carriers, especially electrons, in the channel region to generate charge carriers of sufficient kinetic energy (channel hot electrons) to penetrate the confinement layer and to be trapped in the memory layer. Source and drain regions are provided at both ends of the channel region to apply the accelerating electric voltage.
The threshold voltage of the transistor structure is sensed when the programmed state of the memory cell is read. It is possible to store bits at both channel ends by the application of reverse operating voltages. This means that two bits can be programmed in each charge-trapping memory cell. Examples of charge-trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide of the semiconductor material and the memory layer is a nitride of the semiconductor material, usually silicon.
A publication by B. Eitan et al., “NROM: a Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” in IEEE Electron Device Letters, volume 21, pages 543 to 545 (2000), which is incorporated herein by reference, describes a charge-trapping memory cell with a memory layer sequence of oxide, nitride and oxide which is especially adapted to be operated with a reading voltage that is reverse to the programming voltage (reverse read). The oxide-nitride-oxide layer sequence is especially designed to avoid the direct tunneling regime and to guarantee the vertical retention of the trapped charge carriers. The oxide layers are specified to have a thickness of more than 5 nm.
A type of field effect transistor is formed in a so-called finfet structure, in which the channel region and the source and drain regions are arranged in a ridge or fin at a surface of a semiconductor substrate. The gate electrode is applied to the fin either on the top, at a sidewall or in bridge-like fashion across the fin; and the direction of the channel is parallel to the longitudinal extension of the fin.